This invention relates to a self-routing exchange and, more particularly, to a self-routing exchange in which the amount of hardware can be reduced and which can be enlarged in scale (extended) with ease.
There is increasing demand not only for audio communication and data communication but also for multimedia communication in which moving pictures are transmitted as well as audio and data, and a B-ISDN (broadband-ISDN) switching technique, which is based upon an asynchronous transfer mode (ATM), is now being put to practical use as means for realizing such broadband communication.
ATM transmission converts all information into fixed information, which is referred to as a "cell", cell transfers the information at high speed. More specifically, in ATM transmission, a line is allocated to a plurality of calls by establishing a logical link on a physical line in multiplexed fashion. Moving-picture data or audio data from a terminal corresponding to each call is broken down into fixed-length information units (referred to as "cells"), and the cells are transmitted over a line sequentially to realized multiplexing.
As shown in FIG. 11, a cell is composed of fixed-length block of 53 bytes of which five bytes constitute a header HD and 48 bytes constitute an information field DT. The header HD contains a call-identifying virtual channel identifier (VCI) so that the destination will be known even after the data has been separated into blocks, a virtual path identifier (VPI) which specifies the path, a generic flow control (GFC) used in flow control between links, payload type PT and a header error control (HEC) for correcting errors.
FIG. 12 is a diagram showing the general configuration of an ATM network useful in describing ATM transmission. Shown in FIG. 12 are ATM terminals 1a, 1b and an ATM network 3. The ATM network 3 has an information network 3a that transmits data cells and a signal network 3b that transmits control signals. Call processing processors (CPUs) 3d-1.about.3d-n of ATM exchanges 3c-1.about.3c-n in the information network 3a are connected to the signal network 3b.
When a call operation is performed so that the originating terminal 1a may call the terminating terminal 1b, a cell assembler within the originating terminal 1a partitions a set-up message (data which includes the originating number, the terminating number, the type of terminal, the average cell speed and the maximum cell speed, etc.) into cell units, attaches a signal VCI (determined in advance for each terminal) to each item of partitioned data to form a signal cell and sends the signal cells to the ATM network 3.
If a signaling device of the ATM exchange (on the originating side) 3c-1 receives a signal cell, the signaling device assembles the information contained in the signal cell and notifies the CPU 3d-1 of the information. The CPU executes such call processing as processing for analyzing calling-party service, billing processing and processing for interpreting digits on the side of the terminating party, decides a virtual path (VPI) and call identifying information (VCI) on the basis of the reported average cell speed and maximum cell speed and, in accordance with a No. 7 protocol, sends the next relay exchange 3c-2 connection information, such as the originating number, terminating number, VPI, VCI and other data, via the signal network 3b. The relay exchange 3c-2 executes processing similar to that of the originating terminal 3c-1. Thereafter, processing similar to that described is performed until finally a path from the originating exchange 3c-1 to the ATM exchange (the exchange on the terminating side) 3c-n, to which the terminating terminal is connected, is decided as well as the relay ATM exchanges 3c-2, 3c-3 . . . . If the terminating exchange 3c-n receives connection information containing the originating number, the terminating number and the VCI of the higher-order ATM exchange 3c-3, then the exchange 3c-n assigns a prescribed VCI to the terminating terminal 1b and it is determined whether the terminating terminal 1b is capable of communicating. If communication is possible, then the signal network 3b notifies the originating exchange 3c-1 of the fact that communication is possible and the originating exchange assigns a prescribed VCI to the originating terminal 1a.
Each of the ATM exchanges 3c-1.about.3c-n on the paths registers the following, for each path, in an internal routing table in a form correlated with the VCI of the higher-order ATM exchange: (1) information (referred to as routing information or tag information) for specifying the outgoing highway of the cell having the particular VCI, and (2) a new VCI and new VPI, which are added on to the outputted cell.
Thus, when a path is formed between the originating terminal 1a and the terminating terminal 1b, the two terminals send and receive call cells and answer cells and verify the communication procedure in mutual fashion. Thereafter, the originating terminal 1a breaks down data to be transmitted into prescribed byte lengths, adds on a header containing the allocated VCI to produce a cell and sends the cell to the ATM network 3. When each of the ATM exchanges 3c-1.about.3c-n is supplied with an input cell from the higher-order exchange via the prescribed incoming highway, the ATM exchange refers to its own routing table to replace the VPI/VCI of the inputted cell and sends the cell out on the prescribed outgoing highway based upon the tag information. As a result, the cell outputted by the originating terminal 1a arrives at the terminating exchange 3c-n via the path that has been decided by call control. The terminating terminal 3c-n refers to its routing table, changes the VCI attached to the inputted cell to the VCI allocated to the terminating terminal and then sends the cell to the line to which the terminating terminal 11b is connected.
Thereafter, the originating terminal 1a sends cells to the terminating terminal 1b in successive fashion and the terminating terminal 1b assembles the information field DT contained in the received cells, thereby restoring the original data.
The foregoing relates to a case for dealing with one call. However, by changing the mutually held VCI values at both ends of each line between the terminal and ATM exchange and between the mutually adjacent ATM exchanges, logical links conforming to a number of calls can be established on one line. As a result, high-speed multiplexed communication may be realized. In accordance with an ATM system, information from information sources such as moving pictures, data and audio having different transmission rates can be multiplexed. As a consequence, a single transmission line can be used in a very effective manner. Moreover, re-transmission control and complicated communication procedures such as implemented by software through packet switching are no longer necessary and it is possible to achieve ultra-high-speed data transmission on the order of 150 to 600 Mbps.
Further, an ATM exchange has a buffering function. In a case where a large number of calls are generated in an ATM exchange or terminating terminal, the buffering function makes it possible to accept the calls and send them to the terminating terminal without making the originating terminal wait. For example, when calls directed to the terminating terminal 1b are generated from a large number of terminals simultaneously and, as a result, the line between the exchange 3c-n on the terminating side and the terminating terminal 1b is no longer vacant, cells not sent to the terminating terminal are generated. In such case, the exchange 3c-n on the terminating side buffers the cells not sent and transmits the cells when the line becomes available, thereby making it possible to accept the calls and send them to the terminating terminal without making the transmitting terminal wait.
FIG. 13 is a diagram showing the construction of a self-routing ATM exchange useful in describing the buffering function of such ATM exchange. The self-routing ATM exchange has one basic switching unit SWU, a control-information add-on unit CIAU and a call processing CPU (call controller) CPR. It should be noted that this ATM exchange has a multistage buffer-type ATM channel configuration in which a plurality of paths exist between one given incoming highway (input port) and one given outgoing highway (output port) and a three-stage self-routing switch module is provided between each incoming highway and outgoing highway.
The basic switching unit SWU has input-stage self-routing switch modules SRM.sub.11 .about.SRM.sub.13, intermediate-stage self-routing switch modules SRM.sub.21 .about.SRM.sub.23 and output-stage self-routing switch modules SRM.sub.31 .about.SRM.sub.33. Thus, the unit has a multiple-link (three-link in FIG. 13) construction. Primary links are indicated at L.sub.11 18 L.sub.33, and secondary links are shown at M.sub.11 18 M.sub.33. The input terminals of the input-stage self-routing switch modules SRM.sub.11 .about.SRM.sub.13 are connected to incoming highways #1.about.#9 via the control-information add-on unit CIAU, the output terminals of the input-stage self-routing switch modules SRM.sub.11 .about.SRM.sub.13 are connected to the intermediate-stage self-routing switch modules SRM.sub.21 .about.SRM.sub.23, the output terminals of the intermediate-stage self-routing switch modules SRM.sub.21 .about.SRM.sub.23 are connected to the output-stage self-routing switch modules SRM.sub.31 .about.SRM.sub.33, and the output terminals of the output-stage self-routing switch modules SRM.sub.31 .about.SRM.sub.33 are connected to outgoing highways #1.about.#9.
The control-information add-on unit CIAU has add-on circuits AC1.about.AC9, which correspond to the incoming highways #1.about.#9, for adding on routing information and the like. The add-on circuits AC1.about.AC9 add routing headers RH (see FIG. 14) onto the cells which have entered from the corresponding incoming highways, replace the VCI contained in each cell and send the cells out to the basic switching unit SWU.
The call controller CPR performs call control at the time of an outgoing call in order to decide the VCI of the call, decide the routing header in conformity with the location of the terminating terminal and write this information (the routing header and the VCI) in a routing table (not shown) of the add-on circuit to which the cell conforming to the call was applied. Furthermore, the control information (routing header and VCI) decided is written in the routing table in correlation with the VCI of the higher-order ATM exchange. The routing header RH (FIG. 14) has three items of routing information RH.sub.1, RH.sub.2 and RH.sub.3. The routing information RH.sub.1 indicates the number of the primary link, namely the output terminal number of the input-stage module; the routing information RH.sub.2 indicates the number of the secondary link, namely the output terminal number of the intermediate-stage module; and the routing information RH.sub.3 indicates the number of the outgoing highway, namely the output terminal number of the output stage.
When call control ends and cell enter the prescribed incoming highways via the higher-order ATM exchange, the add-on circuits AC1.about.AC9 connected to the incoming highways go to the routing tables to read out the control information (routing headers RH and VCI) conforming to the VCIs that have been added on to the input cells. Routing headers are then added on to the cells, the VCIs of the cells are replaced by the VCIs read out and the cells are sent out to the basic switching unit SWU. FIG. 14 shows an example of the format of the information outputted by each of the add-on circuits AC1.about.AC9.
The module SRM.sub.ij of each stage uses the routing header RHi to route the cells to the pertinent links, namely to the prescribed output terminals, whence the cells are finally transmitted from the prescribed outgoing highways. It should be noted that the routing headers are removed by a post-processing circuit (not shown) before they are transmitted to the outgoing highways.
FIG. 15 is a circuit diagram showing a specific example of a self-routing switch module (SRM1).
The module includes control-information detecting circuits I.sub.1 .about.I.sub.3, transmission-information delay circuits D.sub.1 .about.D.sub.3, demultiplexers DM.sub.1 .about.DM.sub.3 and control-information decoder circuits DEC.sub.1 .about.DEC.sub.3. These components construct a cell distributor CELD. The module further includes buffer memories, e.g., FIFOs (first-in first-out) FM.sub.11 .about.FM.sub.33, selectors SEL.sub.1 .about.SEL.sub.3 and arrival-order management FIFOs A0M.sub.1 .about.AOM.sub.3. The arrival-order management FIFOs A0M.sub.1 .about.AOM.sub.3 are connected to the output terminal of each of the control-information decoder circuits DEC1.about.DEC3, store the orders of arrival of the cells at the corresponding three buffer memories FM.sub.11 .about.FM.sub.13, FM.sub.21 .about.FM.sub.23 and FM.sub.31 .about.FM.sub.33 and controls the corresponding selectors SEL1.about.SEL3 to read the cells out of the three buffers in the order in which the cells arrived and transmit the cells to outgoing highways #1.about.#3.
The transmission information which enters the input terminals #1.about.#3 has the format shown in FIG. 14. The detecting circuit I.sub.i (i=1.about.3) extracts the control information contained in this signal and sends the control information to the decoder circuit DEC.sub.i (i=1.about.3). The control information has the routing header RH.sub.1 for the input stage, the routing header RH.sub.2 for the intermediate stage and the routing header RH.sub.3 for the output stage. Depending upon the stage number of the self-routing switch module SRM, the detecting circuit I.sub.i detects the pertinent routing information RH.sub.1 .about.RH.sub.3 and applies the information to the decoder circuit DEC.sub.i as an input.
If the entered routing header RH.sub.i indicates output terminal #j (j=1.about.3), the decoder circuit DEC.sub.i operates the demultiplexer DM.sub.i by a changeover signal S.sub.i to send the transmission information to the FIFO memory FM.sub.ji. For example, if the routing header RH contained in the information which has entered from the input terminal #1 indicates output terminal #2, the decoder circuit DEC.sub.1 operates the demultiplexer DM.sub.1 to apply the information from the input terminal #1 to the FIFO memory FM.sub.21. The arrival-order management FIFO (AOM.sub.i) is connected to the output terminal of each of the control-information decoder circuits DEC.sub.1 .about.DEC.sub.3 and stores the order in which the cells arrive at the corresponding three buffer memories FM.sub.i1 .about.FM.sub.i3. For example, if the cells arrive in the order of buffer memory FM.sub.11 .fwdarw.FM.sub.12 .fwdarw.FM.sub.13 .fwdarw.FM.sub.12 .fwdarw.. . . , buffer-memory identification numbers are stored in the arrival-order management FIFO (AOM.sub.1) in the cell-arrival order 1.fwdarw.2.fwdarw.3.fwdarw.2.fwdarw.. . . . Thereafter, the arrival-order management FIFO (AOM.sub.i) controls the selector SEL.sub.i to read the cells out of the three buffer memories FM.sub.i1 .about.FM.sub.i3 in the order in which they arrived and transmit the cells to outgoing highway #i.
By thus providing each FIFO memory FM.sub.ij with a capacity for plural cells, a buffering function is obtained so that it is possible to cope adequately with cases in which there is a temporary increase in the transmission data. Further, since cells are read out of the buffer memories FM.sub.i1 .about.FM.sub.i3 in the order in which they arrived, equal numbers of cells are pooled by the buffer memories FM.sub.i1 .about.FM.sub.i3 and a situation in which the buffer memories overflow and cells are discarded is eliminated.
FIG. 16 is a simplified representation of a self-routing switch module. The buffer memories FM.sub.11 .about.FM.sub.mm are arranged at the intersections of m-number of input links and m-number of output links. The self-routing switch module of FIG. 15 corresponds to the portion enclosed by the dashed line in FIG. 16.
Thus, as set forth above, an ATM exchange (ATM switching system) is a system which performs switching in VCI/VPI units within a cell header. In order to enlarge the scope of such a N.times.N ATM exchange having the numbers N of incoming highways and the numbers N of outgoing highways, a method (first method) of increasing the numbers N has been considered. According to this method, however, when N is increased, the amount of necessary hardware (modules) increases in proportion to N.sup.2 ; hence, the larger N is made, the greater the amount of hardware required.
Further, a method (second method) of connecting n.times.n modules in multiple stages has been considered as a method of enlarging the scope of the system. FIG. 17 illustrates a case in which mn.times.mn ATM switches are arranged in parallel by providing three stages of n.times.n ATM switches SW.sub.i1 .about.SW.sub.i3 (i=1.about.m) in m rows. The outgoing highways of each ATM switch in each stage are divided into m sets of n/m highways each and enter each of m-number of ATM switches constituting the next stage. In accordance with the composition of multiple stages, the amount of hardware is m.multidot.(3n.sup.2). For example, in case that 8n.times.8n ATM switch in which m equals 8 is composed by the second method, an amount of hardware conforming to 24n.sup.2 is required. With the first method, on the other hand, an amount of hardware conforming to 64n.sup.2 is required. Thus, the second method is advantageous in that the amount of hardware required is reduced in comparison with the first method.
According to the second method, however, the outgoing highways of the ATM switches of each stage must be divided up into m sets of n/m highways each and wiring must be provided in such a manner that these highways enter each of the m-number of ATM switches of the next stage. Consequently, when m is changed in order to enlarge the scale of the ATM switches, the wiring must also be changed. This means that extending the system is very troublesome.
Another problem is that signals from an STM (synchronous transfer mode) network cannot be introduced to an ATM network or vice versa to enable simple communication between the respective terminals.